This invention relates to a digital phase-locked loop circuit or delay-locked loop circuit. More particularly, this invention relates to such a circuit having improved resolution.
Feedback loop circuits, including phase-locked loops (PLLs) and delay-locked loops (DLLs), are well known. In such circuits, an output signal is fed back to a detector (e.g., a phase-frequency detector in a PLL or a phase detector in a DLL) that also samples a reference signal. If the output does not bear the desired relationship to the reference signal, the detector generates a signal that causes the output signal generator (e.g., a variable frequency oscillator in a PLL or a variable delay line in a DLL) to vary its output to bring it closer to the desired relationship. This continues until the output signal locks to the reference signal. In a digital loop circuit, the signal generated by the detector is converted by a digital controller into a digital control word that conveys to the output signal generator the amount of delay required to achieve a signal lock.
For frequency synthesis, the feedback loop may include a feedback counter with an integer value N that has the effect of multiplying the output frequency of the signal by N. This is achieved by counting N cycles for each reference cycle. In the case of a digital loop circuit, assuming that the loop circuit (i.e., its delay element) has a certain intrinsic temporal resolution Δt, the effective resolution of the loop circuit becomes NΔt. This degrades the locking performance of the digital loop circuit or, alternatively, requires much higher precision components to achieve the same resolution.
It therefore would be desirable to be able to use a feedback counter for frequency synthesis in a digital loop circuit while maintaining the intrinsic resolution of the circuit.